Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and/or other tasks related to both analog and digital electrical signals. Most common among these are MOSFETs, wherein a metal or (doped) polysilicon gate contact or electrode is energized to create an electric field in an underlying channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body.
The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric or gate oxide, such as silicon dioxide (SiO2), is formed over the channel region to physically separate the gate electrode from the substrate, and more particularly the channel region. A patterned gate electrode and gate dielectric is commonly referred to as a gate structure or stack.
The gate dielectric has electrically insulative properties and, as such, serves to retard the flow of large electrical currents between the gate electrode and the source/drain regions or channel of the substrate when a voltage is applied to the gate contact. The gate dielectric also serves to allow the applied gate voltage to set up an electric field in the channel region in a controllable manner.
A continuing trend in the manufacture of semiconductor products is toward a steady reduction in the size of electrical devices (known as scaling), together with improvements in device performance in terms of device switching speed, power consumption, reliability, etc. New materials and processes have been developed and employed in silicon processing technology to accommodate these requirements, including the ability to pattern and etch smaller device features. Recently, however, electrical and physical limitations have been reached in the thickness of gate dielectrics, particularly those formed of silicon dioxide.
By way of example, FIG. 1 illustrates a conventional complementary MOS (CMOS) device 2 with PMOS and NMOS type transistor devices 4 and 6, respectively, formed in or on a silicon substrate 8. Isolation structures 10, such as shallow trench (oxide) isolation structures (STI), are formed within the substrate 8 to electrically isolate the devices from one another as well as from other surrounding devices. For example, one or both of the transistors may be included as part of an integrated circuit or used in any other appropriate manner.
The substrate 8 in the above example is lightly doped p-type silicon with an n-well 12 formed therein under the PMOS transistor 4. The PMOS device 4 includes two laterally spaced p-doped source/drain regions 14a and 14b with a channel region 16 located therebetween in the n-well 12. A gate is formed over the channel region 16 comprising an SiO2 gate dielectric 20 overlying the channel 16 and a conductive polysilicon gate contact structure 22 formed over the gate dielectric 20.
The NMOS device 6 includes two laterally spaced n-doped source/drain regions 24a and 24b outlying a channel region 26 in the substrate 8 (or alternatively a p-well region (not shown)) with a gate formed over the channel region 26 comprising an SiO2 gate dielectric layer 30 and a polysilicon gate contact 32, where the gate dielectrics 20 and 30 may be patterned from the same oxide layer. Both the PMOS device 4 and the NMOS device 6 include sidewall spacers 18 that aid in doping the respective source/drain regions 14a, 14b and 24a, 24b. 
Referring to the NMOS device 6, for example, the resistivity of the channel 26 may be controlled by the voltage applied to the gate contact 32, where changing the gate voltage changes the amount of current through channel 26. The gate contact 32 and the channel 26 are separated by the SiO2 gate dielectric 30, which is an insulator. The gate dielectric, thus, allows little or no current to flow between the gate contact 32 and the channel 26. The gate dielectric 30 allows the gate voltage at the contact 32 to induce an electric field in the channel 26, by which the channel resistance can be controlled by the applied gate voltage.
MOSFET devices produce an output current proportional to the ratio of the width over the length of the channel (W/L), where the channel length is the physical distance between the source/drain regions (e.g., between regions 24a and 24b in the device 6) and the width runs perpendicular to the length (e.g., perpendicular to the page in FIG. 1A). Thus, scaling the NMOS device 6 to make the width narrower may reduce the device output current. Previously, this characteristic has been accommodated by decreasing the channel length and decreasing the thickness of gate dielectric 30, thus bringing the gate contact 32 doser to the channel 26.
Additionally, the thickness and dielectric constant of the gate dielectric layer 30 are typically chosen to create a gate capacitance appropriate for a particular use of the transistor 6, where the gate capacitance, among other things, controls the formation of the electrical field in channel region 26. The gate capacitance is directly proportional to the dielectric constant of gate dielectric layer 30 and inversely proportional to the thickness of gate dielectric layer 30. Therefore, as the other features of transistor 6 are scaled down, the thickness of gate dielectric layer 30 may also be scaled down proportionally to maintain an appropriate gate capacitance (assuming the dielectric constant of the material remains the same).
However, making the gate dielectric layer 30 thinner can have undesirable results, particularly where the gate dielectric 30 is SiO2. One shortcoming of a thin SiO2 gate dielectric 30 is increased gate leakage currents due to tunneling through the oxide 30. Additionally, since the films are literally formed from a few layers of atoms (monolayers), very precise process controls are required to uniformly and repeatably produce the layers. Uniform coverage is important because device parameters may change based upon the presence or absence of even a single monolayer of dielectric material. Also, a thin SiO2 gate dielectric layer 30 provides a poor diffusion barrier to dopants. In this manner, boron, for example, may be allowed to penetrate into and contaminate the underlying channel region 16 during doping of an overlying poly-silicon gate.
Consequently, recent efforts involving MOSFET device scaling have focused on alternative dielectric materials that can be made thicker than scaled silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO2, (which is about 3.9). The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT), because, while the alternative layer may be thicker, it still provides the equivalent electrical effect of a much thinner layer of SiO2.
Accordingly, high-k dielectric materials can be utilized to form gate dielectrics, where the high-k materials facilitate a reduction in device dimensions while maintaining a consistency of desired device performance. By way of example, conventional gate dielectrics (e.g., of silicon oxide (SiO2)) can have thicknesses of about 1-3 nanometers, whereas high-k gate dielectrics have thicknesses on the order of 2-10 times greater, yet exhibit comparable electrical performance to the thinner SiO2. The larger thickness tends to minimize leakage through the gate dielectric, among other things.
Referring to FIG. 2, one proposed alternative structure is illustrated, in which a high-k gate dielectric material 30′ is used to form a gate dielectric layer in an NMOS device 6′. A conductive gate electrode structure 32′ is formed over the high-k dielectric layer 30′. While such a high-k dielectric layer 30′ assists in mitigating of some of the issues encountered with device scaling, other issues may persist, however. For example, hydrogen and/or hydrogen containing compounds are commonly utilized in many of the stages of semiconductor fabrication, and hydrogen can react with high-k dielectric materials such as hafnium oxide and adversely affect the construction and/or electrical properties thereof.
Hydrogen based precursors, such as SiH4, for example, are used extensively in producing epitaxial silicon, polycrystalline silicon and certain dielectrics, such as Si3N4 and SiO2. These fabrication processes expose the high-k dielectrics to high concentrations of hydrogen which can etch, embrittle or otherwise react with the high-k dielectric materials to reduce or otherwise adversely affect the high-k materials. Additionally, atomic hydrogen (e.g., H) is often produced in semiconductor fabrication processes as certain (transition) metals utilized in the process are known to “crack” hydrogen gas (H2). Atomic hydrogen is a strong etchant of silicon and silicon based compounds, and thus may undesirably reduce many high-k dielectric materials.
Hydrogen can thus reduce the high-k dielectric 30′ and can also create point defects 50′ therein. Such defects 50′ can counteract or negate some of the positive aspects of high-k materials by potentially reducing the electrical thickness of the high-k material 30′ and increasing the leakage path through the high-k dielectric at these defects, thus leading to the aforementioned issues at the contaminated locations 50′. Such defects can also serve as sinks or reservoirs for dopants and/or other electrically active impurities that can fill in the defects 50′ and degrade the electrical properties of the dielectrics, including the reliability thereof.
Further, such defects 50′ disrupt the uniformity of the high-k dielectric material 30′ which can adversely affect the operation of the transistor 6′ by, among other things, disrupting electromagnetic fields that are developed between the gate electrode 32′ and the source 24a′, drain 24b′ and/or channel 26′ regions of the transistor when a bias voltage is applied to the gate electrode 32′. This affects the current flowing through the transistor 6′ (e.g., Ion−Ioff), among other things. It will be appreciated that the defects 50′ depicted in FIG. 2 are merely illustrative and that such defects may have a significantly different physical manifestation in reality.